1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device, in which the number of data lines can be reduced, using a bi-directional internal gate drive circuit.
2. Discussion of the Related Art
Efforts have recently been made to research flat panel display devices such as liquid crystal displays (LCDs), plasma display panels (PDPs), electro-luminescent displays (ELDs), vacuum fluorescent displays (VFDs), and the like. Some types of such flat panel display devices are being practically applied to various appliances for display purposes.
LCDs have been used as a substitute for cathode ray tubes (CRTs) in association with mobile image display devices owing to their characteristics and advantages superior picture quality, lightness, thinness, and low power consumption. Various applications of LCDs are being developed in association with not only mobile image display devices such as laptop computer monitors but also TV monitors to receive and display broadcast signals.
FIG. 1 is a block diagram showing a general active matrix liquid crystal display (LCD) device. As shown in FIG. 1, the general active matrix LCD includes a liquid crystal display panel 1 for displaying images. In the vertical and horizontal end portions of the liquid crystal display panel 1 are provided, respectively, a signal line drive circuit 2 and a scan line drive circuit 3 for driving the liquid crystal display panel 1. Control signals for controlling the signal line drive circuit 2 and the scan line driver circuit 3 are generated from a timing generation circuit 5. Various control signals are generated from a dot clock (CLK), a horizontal synchronization signal (HSYNC), and a vertical synchronization signal (VSYNC) inputted from the outside. In addition, depending on the type of interface between the LCD panel and the input of the signal line drive circuit 2, data processing may need to be performed in order to arrange data according to assigned commands. For this purpose, a data processing circuit 4 may be provided, which is also controlled through the timing generation circuit 5. Usually, the data processing circuit 4 and the timing generation circuit 5 are developed in an integrated form as an ASIC (application specific integrated circuit).
The above-mentioned general liquid crystal display device generally includes a liquid crystal display panel for displaying an image signal and a drive circuit for applying drive signals to the liquid crystal display panel from an external source.
Although not shown in FIG. 1, the liquid crystal display panel 1 comprises two transparent substrates (glass substrates) bonded to each other so as to have a certain space between the two transparent substrates. Located within this space is a liquid crystal layer. In one of the two transparent substrates are formed a plurality of gate lines G1, G2, G3, . . . , Gn arranged at certain regular intervals, a plurality of data lines S1, S2, S3, . . . , Sn arranged at certain regular intervals perpendicularly to the gate lines, a plurality of pixel electrodes formed in array pixel areas, arranged in rows and columns, defined by the gate lines, the data lines, and a plurality of thin film transistors (TFT) The TFTs may be located at the intersections of the gate lines and the data lines for applying the data line signals to pixel electrodes according to the gate line signals. Located in the other transparent substrate are a color filter layer, a common electrode (VCOM), and a black matrix layer.
As a turn-on signal is sequentially applied to each gate line, a data signal is applied to pixel electrodes corresponding to the gate line. The biased pixels cause an image to be displayed.
In the above-constructed TFT LCD device, TFTs are employed as switching elements for turning on and off the pixels inside the device. Switching the TFTs on and off switches corresponding pixels on and off.
In a general TFT liquid crystal display device, cells constituting pixels are arranged in the form of an array with the pixels arranged in rows and columns. Each cell is formed of a switching TFT, a liquid crystal cell, and a storage capacitor (CSTG). The sources of the TFTs are connected in common in columns to form data lines S1 to Sn, which are connected to a source driver at connections S1′, S2′, . . . , SN′. The gates of the TFTs are connected in common in rows to form gate lines G1 to GM, which are connected to a gate driver at connections G1′, G2′, . . . , Gn′. In this manner, an N×M resolution (for example, SVGA (800×600), XGA (1024×768), UXGA (1600×1200)) is realized in the display devices.
The source driver is also known as a data driver, a column driver, or a signal line drive circuit, and the gate driver is also referred to as a row driver, a scan driver, or a scan line drive circuit. Hereinafter, the source driver is referred to as a “signal line drive circuit,” and the gate driver is referred to as a “scan line driver circuit.”
One side of the liquid crystal cell is connected to the TFT drain through the pixel electrode, and the other side is connected to a common electrode. The pixel electrode is formed of a transparent conductive indium tin oxide (ITO). When an on-signal is applied to the TFT gate, a signal voltage applied through the signal line drive circuit is applied to the liquid crystal cell, and the common electrode, also formed of ITO, applies a common voltage (VCOM) to the liquid crystal cell. Storage capacitors (CSTG) function to retain signal voltages applied to the pixel electrodes (pixel ITO) for a certain period of time. These storage capacitors (CSTG) also control the light transmissivity of individual pixels by changing the arranged states of liquid crystal cells through charging and discharging. One side of the storage capacitor (CSTG) may be connected to a separate electrode or a gate electrode. A structure, in which the storage capacitor is connected with a gate electrode, is referred to as a storage-on-gate structure.
Recently, an LCD device employing TFTs has been used as a display device for laptop computers, and therefore cost reduction is desired. One way to realize a low-price LCD device is to reduce the material cost. Additionally, the cost reduction of a driver integrated circuit (IC) for driving signal lines of a liquid crystal panel can reduce the production cost of the entire LCD device. Signal line driver ICs account for most of the material cost of an LCD device because of their advanced operational function and the large number of driver ICs that are required. For example, where one driver IC provides 240 outputs, 10 driver ICs are needed for an SVGA panel. The reduction in the number of driver ICs has been proposed in Japanese Laid-open Patent Publication Nos. 3-38689, 5-265045, and 6-148680. All of these approaches attempt to cut the number of the signal driver ICs in half by allowing neighboring pixels to share the signal lines in the liquid display panel.
FIG. 2 shows a portion of a circuit utilizing a conventional technique for cutting in half the number of signal drivers used in a conventional LCD device. FIG. 3 shows an operation waveform for the LCD circuit of FIG. 2.
As shown in FIG. 2, the conventional LCD device comprises a plurality of gate lines arranged in one direction; pairs of two neighboring pixels (first and second pixels (A, B) (C, D)) connected to one data line; a first transistor T1 receiving a signal from each gate line which turns the transistor on or off; a second transistor T2, receiving a signal from a subsequent gate line, which turns transistor T2 on or off, such that when transistors T1 and T2 are turned on a data signal transmitted through the data line is transmitted to a first pixel; a third transistor T3 receiving a signal from the gate line, which turns transistor T3 on or off, such that when transistor T3 is turned on, a data signal transmitted through the data line is transmitted to a second pixel; and a storage capacitor Cst connected between a previous gate line and each pixel.
The above structure is a data line sharing (DLS) drive structure for driving two neighboring pixels through one data line. In the LCD device using the above DLS driving scheme, one data line is used to apply a data signal to two neighboring pixels and thus the number of data driver ICs can be cut in half.
For DLS driving, a waveform different from conventional waveforms is required. As shown in FIG. 3, a gate waveform having a half-period output waveform before one period of output waveform is employed. A waveform applied to one gate line consists of two waveforms, and the period of a previous waveform is half that of the subsequent waveform.
The operating principle of the above LCD device will now be explained with reference to the figures. As shown in FIGS. 2 and 3, in the case where a gate signal is sequentially applied to the gate lines G(n), G(n+1), G(n+2), if, at the t1 section, one period of “high” signal is applied to the gate line G(n+1) and a half period of “high signal” is applied to the gate line G(n+2), the first and third transistors T1 and T3 receive the gate line G(n+1) signal and are turned on. As the first transistor T1 is turned on, the second transistor T2 receives the gate line G(n+2) signal and is turned on. Thus, a data signal is applied simultaneously, via data lines D(m), D(m+1), D(m+2), etc. to the first and second pixels A and B.
At the t2 section, after a half-period, the second transistor T2 is turned off because gate line G(n+2) is at a low signal, and the first and third transistors T1 and T3 remain turned on. Thus, the first pixel A retains the already-applied data signal, and the second pixel B can receive another data signal. In this manner, using one data line, two different data signals can be sequentially applied to two neighboring pixels.
As described above, using a next gate line signal having a half period, a data signal can be applied selectively to two different pixels adjacent to each other. This driving method can cut the number of data lines in half, as compared with a general data driving method where one data line corresponds to one pixel, thus making it possible to cut the number of data driver ICs in half.
However, the application of this data line sharing (DLS) method necessitates a separate gate driver IC, which can successively output a half-period waveform and one period waveform, rather than a general wave. Therefore, even if the number of the data lines is cut in half, a separate gate driver IC must be provided, thus resulting in a limitation in cost reduction.
A circuit utilizing a second conventional technique for cutting in half the number of signal drivers used in a conventional LCD device and its operational waveform diagram are shown in FIGS. 4 and 5, respectively. As shown in FIG. 4, the liquid crystal display panel includes an n×m array of pixel electrodes, where n and m are integers not less than two. Two adjacent odd and even-numbered pixels along a horizontal or row direction share one data line, which is extended in vertical direction. Connected to the shared data line (S1, S2, . . . , Sn/2) is the drain of a TFT, which is a switching element connected to each pixel. The number of data lines is half that of the horizontally arranged pixels (e.g., n/2).
For explanation and without limitation, the gates of the two neighboring TFTs, may be referred to as odd-numbered TFTs (dm1, dm3, dm5, . . . , dm(n−1)) and as even-numbered TFTs (dm2, dm4, dm6, . . . , dmn), are connected respectively to two different gate lines (G1, G2, . . . , G2n), which are assigned to a horizontal display line that extends in horizontal direction. The number of gate lines is twice the number of vertically arranged pixels (e.g., 2m).
According to the above configuration, however, in an odd-numbered display line (m=1, 3, 5, etc.), the TFT gate of a horizontally odd-numbered pixel is connected to an odd-numbered gate line, and the TFT gate of a horizontally even-numbered pixel is connected to an even-numbered gate line. Further, in an even-numbered display line (m=2, 4, 6, etc.), the TFT gate of a horizontally odd-numbered pixel is connected to an even-numbered gate line, and the TFT gate of a horizontally even-numbered pixel is connected to an odd-numbered gate line. With respect to an arbitrary horizontally-extended display line with a plurality of (for example, two) gate lines assigned thereto, a horizontally odd-numbered TFT gate is connected to one of the two gate lines and a horizontally even-numbered TFT gate is connected to the other gate line. In a display line adjacent to the above display line, the TFT gates and the gate lines are connected in the opposite manner to the previous one. In other words, the odd-numbered display line and the even-numbered display line are opposite to each other in terms of the connection of the TFT gates to the gate lines.
FIG. 5 shows an operational waveform for the LCD circuit of FIG. 4. A data processing circuit (not shown) receives serially inputted data, and one line portion of the received data is written in a line memory formed in the data processing circuit. According to connections between the TFTs, the data lines, and the gate lines of the panel, the data is divided into two parts corresponding respectively to first and second halves of one horizontal period (1H).
In the first row display line (m=1), the first half data is output to odd-numbered data lines S1, S3, S5, . . . , to form a pattern A. The second half data is output to even-numbered data lines S2, S4, S6, . . . , to form a pattern B.
In the second row display line (m=2), the first half is output to odd numbered data lines S1, S3, S5, . . . , but now forms a pattern B, and the second half is output to even numbered data lines S2, S4, S6, . . . , but now forms a pattern A. From the third row display line through the mth row display line, the data output patterns in the above first and second row display lines are repeated. In this manner, if the data is outputted to the data line, the gate lines sequentially apply a TFT-on voltage to corresponding gate lines G1, G2, G3, . . . , so that desired data is written into desired pixels.
Looking at data line S1, if the gate lines are sequentially turned on from the first gate line G1, the data is sequentially written into pixels d11(A), d12(B), d22(B), d21(A), . . . . Here, (A) and (B) denote the pattern A and B respectively.
Signals outputted from neighboring outputs of the signal line drive circuit have opposite polarities to each other. Considering that the polarity is switched for every output, on completion of writing one frame, the polarity on the screen is alternated at two-pixel intervals in horizontal direction and at one-pixel interval in vertical direction. This differs slightly from dot inversion driving in which all neighboring pixels have opposite polarities. In the sense that one pair of pixels consist of two adjacent pixels, they are regarded to have opposite polarities, thereby alleviating screen flicker due to the difference between positive and negative polarities.
In the above-described conventional LCD device, two gate lines are involved in driving odd-numbered pixels and even-numbered pixels in each display line. Thus, since one display line is driven by means of two gate lines, the LCD device requires twice as many gate lines as an LCD device using one gate line. Accordingly, in order for all the doubled gate lines to be driven during one frame, the charging time for one pixel is reduced to H/2 from 1H, and thus an effective charging time for each pixel cannot be easily achieved.